I Verilog er altid-blokken en af de proceduremæssige blokke. Udsagn inde i en altid-blok udføres sekventielt.
En altid-blok udføres altid, i modsætning til indledende blokke, der kun udføres én gang i begyndelsen af simuleringen. Altid-blokken skal have en følsom liste eller en forsinkelse forbundet med sig
Den følsomme liste er den, der fortæller blokken altid, hvornår kodeblokken skal udføres.
Syntaks
Det Verilog bloker altid følgende syntaks
always @ (event) [statement] always @ (event) begin [multiple statements] end
Eksempler
binær søgning
Symbolet @ efter reserveret ord altid , angiver, at blokeringen vil blive udløst på betingelsen i parentes efter symbol @.
always @ (x or y or sel) begin m = 0; if (sel == 0) begin m = x; end else begin m = y; end end
I ovenstående eksempel beskriver vi en 2:1 mux med input x og y. Det det her er den valgte input, og m er mux-output.
I enhver kombinationslogik ændres output, når input ændres. Når denne teori anvendes på altid blokke, så skal koden i altid blokke udføres, når input- eller outputvariablerne ændres.
BEMÆRK: Det kan drive reg og heltal datatyper, men kan ikke drive wire datatyper.
Der er to typer følsomme lister i Verilog, såsom:
- Niveaufølsom (til kombinationskredsløb).
- Kantfølsom (til flip-flops).
Koden nedenfor er den samme 2:1 mux, men outputtet m er nu en flip-flop udgang.
always @ (posedge clk ) if (reset == 0) begin m <= 0; end else if (sel="=" 0) begin m <="x;" pre> <h4>NOTE: The always block is executed at some particular event. A sensitivity list defines the event.</h4> <h3>Sensitivity List</h3> <p>A sensitivity list is an expression that defines when the always block executed, and it is specified after the @ operator within the parentheses ( ). This list may contain either one or a group of signals whose value change will execute the always block.</p> <p>In the code shown below, all statements inside the always block executed whenever the value of signals x or y change.</p> <pre> // execute always block whenever value of 'x' or 'y' change always @ (x or y) begin [statements] end </pre> <p> <strong>Need of Sensitivity List</strong> </p> <p>The always block repeats continuously throughout a simulation. The sensitivity list brings a certain sense of timing, i.e., whenever any signal in the sensitivity list changes, the always block is triggered.</p> <p>If there are no timing control statements within an always block, the simulation will hang because of a zero-delay infinite loop.</p> <p>For example, always block attempts to invert the value of the signal clk. The statement is executed after every 0-time units. Hence, it executes forever because of the absence of a delay in the statement.</p> <pre> // always block started at time 0 units // But when is it supposed to be repeated // There is no time control, and hence it will stay and // be repeated at 0-time units only and it continues // in a loop and simulation will hang always clk = ~clk; </pre> <p>If the sensitivity list is empty, there should be some other form of time delay. Simulation time is advanced by a delay statement within the always construct.</p> <pre> always #10 clk = ~clk; </pre> <p>Now, the clock inversion is done after every 10-time units. That's why the real Verilog design code always requires a sensitivity list.</p> <h4>NOTE: Explicit delays are not synthesizable into logic gates.</h4> <h3>Uses of always block</h3> <p>An always block can be used to realize combinational or sequential elements. A sequential element like flip flop becomes active when it is provided with a clock and reset.</p> <p>Similarly, a combinational block becomes active when one of its input values change. These hardware blocks are all working concurrently independently of each other. The connection between each is what determines the flow of data.</p> <p>An always block is made as a continuous process that gets triggered and performs some action when a signal within the sensitivity list becomes active.</p> <p>In the following example, all statements within the always block executed at every positive edge of the signal clk</p> <pre> // execute always block at the positive edge of signal 'clk' always @ (posedge clk) begin [statements] end </pre> <h3>Sequential Element Design</h3> <p>The below code defines a module called <strong> <em>tff</em> </strong> that accepts a data input, clock, and active-low reset. Here, the always block is triggered either at the positive edge of the <strong> <em>clk</em> </strong> or the negative edge of <strong> <em>rstn</em> </strong> .</p> <p> <strong>1. The positive edge of the clock</strong> </p> <p>The following events happen at the positive edge of the clock and are repeated for all positive edge of the clock.</p> <p> <strong>Step 1:</strong> First, if statement checks the value of active-low reset <strong> <em>rstn</em> </strong> .</p> <ul> <li>If <strong> <em>rstn</em> </strong> is zero, then output q should be reset to the default value of 0.</li> <li>If <strong> <em>rstn</em> </strong> is one, then it means reset is not applied and should follow default behavior.</li> </ul> <p> <strong>Step 2:</strong> If the previous step is false, then</p> <ul> <li>Check the value of d, and if it is found to be one, then invert the value of q.</li> <li>If d is 0, then maintain value of q.</li> </ul> <pre> module tff (input d, clk, rstn, output reg q); always @ (posedge clk or negedge rstn) begin if (!rstn) q <= 0; else if (d) q <="~q;" end endmodule pre> <p> <strong>2. Negative edge of reset</strong> </p> <p>The following events happen at the negative edge of <strong> <em>rstn</em> </strong> .</p> <p> <strong>Step 1:</strong> First, if statement checks the value of active-low reset <strong> <em>rstn</em> </strong> . At the negative edge of the signal, its value is 0.</p> <ul> <li>If the value of <strong> <em>rstn</em> </strong> is 0, then it means reset is applied, and output should be reset to the default value of 0.</li> <li>And if the value of <strong> <em>rstn</em> </strong> is 1, then it is not considered because the current event is a negative edge of the <strong> <em>rstn</em> </strong> .</li> </ul> <h3>Combinational Element Design</h3> <p>An always block can also be used in the design of combinational blocks.</p> <p>For example, the digital circuit below represents three different logic gates that provide a specific output at signal o.</p> <img src="//techcodeview.com/img/verilog-tutorial/39/verilog-always-block.webp" alt="Verilog Always Block"> <p>The code shown below is a module with four input ports and a single output port called o. The always block is triggered whenever any of the signals in the sensitivity list changes in value.</p> <p>The output signal is declared as type <strong> <em>reg</em> </strong> in the module port list because it is used in a procedural block. All signals used in a procedural block should be declared as type <strong> <em>reg</em> </strong> .</p> <pre> module combo (input a, input b, input c, input d, output reg o); always @ (a or b or c or d) begin o <= ~((a & b) | (c^d)); end endmodule < pre> <p>The signal o becomes 1 whenever the combinational expression on the RHS becomes true. Similarly, o becomes 0 when RHS is false.</p> <hr></=></pre></=></pre></=>
Liste over behov for følsomhed
Altid-blokken gentages kontinuerligt gennem en simulering. Følsomhedslisten giver en vis fornemmelse af timing, det vil sige, at hver gang et signal i følsomhedslisten ændres, udløses altid-blokken.
Hvis der ikke er nogen tidsstyringsudsagn inden for en altid blok, vil simuleringen hænge på grund af en nul-forsinkelse uendelig sløjfe.
Bloker for eksempel altid forsøg på at invertere værdien af signalet clk. Udsagnet udføres efter hver 0-tidsenhed. Derfor udføres det for evigt på grund af fraværet af en forsinkelse i erklæringen.
// always block started at time 0 units // But when is it supposed to be repeated // There is no time control, and hence it will stay and // be repeated at 0-time units only and it continues // in a loop and simulation will hang always clk = ~clk;
Hvis følsomhedslisten er tom, bør der være en anden form for tidsforsinkelse. Simuleringstiden fremskyndes af en forsinkelseserklæring inden for altid-konstruktionen.
always #10 clk = ~clk;
Nu udføres ur-inversionen efter hver 10-tidsenhed. Det er derfor, den rigtige Verilog-designkode altid kræver en følsomhedsliste.
BEMÆRK: Eksplicitte forsinkelser kan ikke syntetiseres til logiske porte.
Bruger altid blok
En altid-blok kan bruges til at realisere kombinations- eller sekventielle elementer. Et sekventielt element som flip flop bliver aktivt, når det er forsynet med et ur og nulstilles.
På samme måde bliver en kombinationsblok aktiv, når en af dens inputværdier ændres. Disse hardwareblokke arbejder alle samtidigt uafhængigt af hinanden. Forbindelsen mellem hver er det, der bestemmer datastrømmen.
En altid blokering er lavet som en kontinuerlig proces, der udløses og udfører en handling, når et signal inden for følsomhedslisten bliver aktivt.
I det følgende eksempel udføres alle udsagn inden for altid-blokken ved hver positive kant af signalet clk
// execute always block at the positive edge of signal 'clk' always @ (posedge clk) begin [statements] end
Sekventielt elementdesign
Nedenstående kode definerer et modul kaldet tff der accepterer datainput, ur og aktiv-lav nulstilling. Her udløses altid blokeringen enten ved den positive kant af clk eller den negative kant af rstn .
1. Urets positive kant
Følgende hændelser sker ved den positive kant af uret og gentages for alle positive kant af uret.
Trin 1: For det første kontrollerer if-sætningen værdien af aktiv-lav nulstilling rstn .
- Hvis rstn er nul, så skal output q nulstilles til standardværdien 0.
- Hvis rstn er en, betyder det, at nulstilling ikke anvendes og bør følge standardadfærd.
Trin 2: Hvis det forrige trin er falsk, så
- Tjek værdien af d, og hvis den viser sig at være én, så inverter værdien af q.
- Hvis d er 0, så bibehold værdien af q.
module tff (input d, clk, rstn, output reg q); always @ (posedge clk or negedge rstn) begin if (!rstn) q <= 0; else if (d) q <="~q;" end endmodule pre> <p> <strong>2. Negative edge of reset</strong> </p> <p>The following events happen at the negative edge of <strong> <em>rstn</em> </strong> .</p> <p> <strong>Step 1:</strong> First, if statement checks the value of active-low reset <strong> <em>rstn</em> </strong> . At the negative edge of the signal, its value is 0.</p> <ul> <li>If the value of <strong> <em>rstn</em> </strong> is 0, then it means reset is applied, and output should be reset to the default value of 0.</li> <li>And if the value of <strong> <em>rstn</em> </strong> is 1, then it is not considered because the current event is a negative edge of the <strong> <em>rstn</em> </strong> .</li> </ul> <h3>Combinational Element Design</h3> <p>An always block can also be used in the design of combinational blocks.</p> <p>For example, the digital circuit below represents three different logic gates that provide a specific output at signal o.</p> <img src="//techcodeview.com/img/verilog-tutorial/39/verilog-always-block.webp" alt="Verilog Always Block"> <p>The code shown below is a module with four input ports and a single output port called o. The always block is triggered whenever any of the signals in the sensitivity list changes in value.</p> <p>The output signal is declared as type <strong> <em>reg</em> </strong> in the module port list because it is used in a procedural block. All signals used in a procedural block should be declared as type <strong> <em>reg</em> </strong> .</p> <pre> module combo (input a, input b, input c, input d, output reg o); always @ (a or b or c or d) begin o <= ~((a & b) | (c^d)); end endmodule < pre> <p>The signal o becomes 1 whenever the combinational expression on the RHS becomes true. Similarly, o becomes 0 when RHS is false.</p> <hr></=></pre></=>